module top(
           input clk_fast,
           input clk_slow,
           input rst_n,
           input signal_in,

           output signal_out
       );
reg signal_r;
reg signal_rr;
always@(posedge clk_fast or negedge rst_n)
	begin
		if (!rst_n)
			{signal_rr, signal_r} <= {2{1'b0}};
		else if (signal_in == 1'b1)
			{signal_rr, signal_r} <= {signal_r, signal_in};
		else
			{signal_rr, signal_r} <= {2{1'b0}};
	end

assign signal_out = signal_rr;
endmodule
